• 12-layer PCI Interface board, 0.063"thick.

• Signal routing on top, bottom and on four internal layers.

• Power and impedance control planes on 6 internal layers.

• 50-ohm single-ended impedance, 100-om differential impedance on eight gigabit channels.

• Optical light pipes transform surface mounted LEDs into front panel indicators.

Significant PCB layout challenges included: an 1152-pin Ball Grid Array packaged Virtex-II Pro, a Parallel Optical link (PAROLI) Gigabit rate optical receiver in a 100-pin BGA package and twin 200-pin SODIMM Double Data Rate Rams (DDR) whose data rates occur on every clock edge meaning the data lines transition at twice the speed of the clock.

The entire design was routed without any blind or buried vias or any microvia drill sizes in order to keep the fabrication costs lower.

The client had no money for fabricating a prototype.  This design had to work out of the box and it did thanks to the design engineer's near flawless schematic and constant attention paid to every application note and layout recommendation for each silicon device on board during the PCB design process.  The board required one wire to correct for a missing connection in the schematic, and that wire was only needed for programming and could be removed afterward.  Despite the gigabit and double data rate signals on board there were no signal integrity issues.